Digital signal detecting and compensating circuit with adjustable window signal

ABSTRACT

In a detecting and compensating circuit of an apparatus for reproducing a digital signal separated by frame synchronizing signals into frames, each having a predetermined frame period, the combination comprising a detecting circuit which detects the frame synchronizing signals and generates respective detection signals in response thereto, a gating circuit which receives the detection signals and which gates the latter in response to gating signals, and a windowing circuit which generates window signals of a predetermined length in response to the detection signals and which supplies the window signals as the gating signals to the gating circuit.

This is a continuation of application Ser. No. 06/443,902, filed Nov.23, 1982 and now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to devices for reproducing a digital signal, andmore particularly, to a frame synchronizing signal detecting andcompensating circuit for use in a reproducing apparatus which generatesa digital signal separated into frames.

2. Description of the Prior Art

An audio signal can be digitally recorded on a disc by a pulse codedemodulation (PCM) system. The audio PCM signal is recorded on a baseband which is not the carrier modulation system (and can be, forexample, amplitude modulation, frequency modulation, or the like.) A runlength limited code has been used to record the audio PCM signal on thedisc. In a run length limited code, a minimum transition intervalT_(min) extends between two pieces data in order to enhance theefficiency of the recording (where T_(min) is the minimum number ofconsecutive bits of the same type.) A maximum transition intervalT_(max) between two data pieces is shortened so that the self clockingaction performed by the reproducing apparatus is more easily performed(where T_(max) is the maximum number of consecutive bits of the sametype).

The digital signal is frequently separated into a number of blocks orframes so that error correction and other processing can be easilyperformed. Usually, each block of data is individually processed in theconversion to analog data. In a digital audio disc, the length of onedata block is made equal to one frame period. Each data block, ofcourse, is provided at its start point with a frame or blocksynchronizing signal.

A bit pattern not used in the run length limited code is ordinarilyselected as the frame synchronizing signal for ease of detection. Oneprior art system takes advantage of the fact that the modulation outputof two maximum transition intervals T_(max) do not occur in the normalmodulation method, and uses as the frame synchronizing signal a bitpattern of two successive maximum transition intervals T_(max). Withrespect to a run length limited code, this means that the framesynchronizing signal is formed by a first interval of continuous "1"sduring the first maximum transition interval T_(max), followed by asecond interval of continuous "0"s during the next maximum transitioninterval T_(max).

However, the frame synchronizing signal is not always properly detectedand processed. Accordingly, a compensating circuit which compensates foran improperly detected and/or processed frame synchronizing signal isgenerally provided in the reproducing apparatus.

The compensating circuit in the reproducing apparatus must accommodate anumber of different kinds of errors. For example, a frame synchronizingsignal can be omitted or "dropped" by a scratch or the like formed onthe surface of the disc. As another example, a pulse form which closelyresembles the frame synchronizing signal can occur in a reproducedsignal. Such a digital signal can be erroneously identified as a framesynchronizing signal, with the result that subsequent data processingoperations are erroneously performed. As a third example, when a digitalaudio disc player is operated in a search mode to access the beginningof an audio signal, the frame synchronizing signal might not bedetected. It is preferable for the frame synchronizing signal to beimmediately identified upon the completion of the search mode, so thatthe audio signal can be correctly reproduced in the normal playbackmode. As a fourth example, the frame period for the digital data canvary.

Conventional compensating circuits for use in reproducing apparatusesrequire a memory which operates at high speed. A majority logic circuitis also used to identify the frame synchronizing signals. In such amajority logic circuit, when a doubtful frame synchronizing pulse occursrepeatedly at the same position in each frame period, the doubtful framesynchronizing pulses cannot be removed.

Reproducing apparatuses for digitally recorded signals generally employa control circuit to control the rotational speed of the disc. Avelocity control circuit controls large fluctuations in the speed of thedisc. A phase control circuit controls minor fluctuations in the speedof the disc since it has a limited lock range. The phase control circuitthus cannot be locked into operation until the speed of the disc isapproximately set by the velocity control circuit. Accordingly, thespeed of the disc must be ascertained before the phase control circuitis switched into operation with the velocity control circuit.

OBJECTS AND SUMMARY OF THE INVENTION

It is an object of the present invention to provide an apparatus forreproducing a digital signal which does not suffer from theabove-described defects in the prior art.

It is another object of the present invention to provide an apparatusfor reproducing a digital signal with a simple compensating circuit forhandling errors which occur in detecting a frame synchronizing signal.

It is another object of the present invention to provide an apparatusfor reproducing a digital signal which does not require a large capacitymemory.

It is still another object of the present invention to provide anapparatus for reproducing a digital signal in which a signal whichoccurs at the same position during successive frame periods and iserroneously identified as a frame synchronizing signal by a detectioncircuit can be removed.

It is still another object of the present invention to provide anapparatus for reproducing a digital signal which can perform optimumframe synchronizing signal compensating operations in accord with morethan one operating mode of the reproducing apparatus.

It is yet a further object of the present invention to provide anapparatus for reproducing a digital signal in which a phase controlcircuit, which makes minor corrections to the speed of the reproducingapparatus, is added to a velocity control circuit, which makes largecorrections to the speed of the reproducing apparatus, in response to acircuit which detects the frame synchronizing signals.

In accord with the present invention, a detecting and compensatingcircuit in an apparatus for reproducing a digital signal separated byframe synchronizing signals into frames, each having a predeterminedframe period, comprises detecting means for detecting the framesynchronizing signals and generating respective detection signals inresponse thereto, gating means receiving the detection signals forgating the latter in response to gating signals, and windowing means forgenerating window signals of a predetermined length in response to thedetection signals and for supplying the window signals as the gatingsignals to the gating means.

The above, and other objects, features and advantages of the presentinvention will be apparent from the following detailed description of anillustrative embodiment thereof which is to be read in connected withthe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a prior art compensating circuitfor frame synchronizing signals in a digital signal;

FIGS. 2A to 2F are time charts illustrating the operation of thecompensating circuit of FIG. 1 when supplied with a digital signalhaving a short period and drop outs of the frame synchronizing signal;

FIGS. 3A to 3F are time charts illustrating the operation of thecompensating circuit of FIG. 1 when supplied with a digital signalhaving a long period and drop outs of the frame synchronizing signal;

FIGS. 4A to 4F are time charts illustrating the operation of thecompensating circuit of FIG. 1 when supplied with a digital signalhaving a doubtful frame synchronizing signal and with a drop out of theframe synchronizing signal, and when supplied with a digital signal froma reproducing apparatus when it is operated in a search mode;

FIG. 5 is a block diagram illustrating a rotational speed control systemused in an apparatus for reproducing a digital signal;

FIGS. 6A to 6O are waveform diagram illustrating the operation of thesystem of FIG. 5;

FIG. 7 is a block diagram illustrating a frame synchronizing signaldetecting and compensating circuit in accord with the present invention;

FIGS. 8A to 8E are time charts illustrating the operation of the circuitof FIG. 7 when supplied with a digital signal having a short period anddrop outs of the frame synchronizing signal;

FIGS. 9A to 9E are time charts illustrating the operation of the circuitof FIG. 7 when supplied with a digital signal having a long period anddrop outs of the frame synchronizing signal; and

FIGS. 10A to .[.10E.]. .Iadd.10F .Iaddend.are time charts illustratingthe operation of the circuit of FIG. 7 when supplied with a digitalsignal having a doubtful frame synchronizing signal, a drop out of theframe synchronizing signal, and when supplied with a digital signal froma reproducing apparatus operated in a search mode.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In a prior art compensating circuit as illustrated in FIG. 1, areproduced digital data signal is supplied to an input terminal 1 and ashift register 2. Shift register 2 has shift stages for n bitscorresponding to the length of a frame synchronizing signal. Data havingn parallel bits are supplied by shift register 2 to a framesynchronizing signal detection circuit or detector 3. The framesynchronizing signal in the reproduced digital data signal is identifiedin frame synchronizing signal detector 3 when the bit pattern of theframe synchronizing signal coincides with a predetermined bit pattern.

The data from shift register 2 are also supplied to a memory unit 4which stores therein one block or frame period of data. The data storedin memory unit 4 is then supplied to a shift register 5 and is delayedby one frame period. Shift register 5 is similar to shift register 2,and has shift stages for n bits so that parallel data of n bits aredelivered from shift register 5 to a second frame synchronizing signaldetection circuit or detector 6 wherein the frame synchronizing signalis detected again (just as in frame synchronizing signal detector 3).The data from shift register 5 is also supplied to a second memory unit7 which is similar to memory unit 4 and stores one block of datatherein. Data stored in memory unit 7 is delayed by one frame period andsupplied to a shift register 8. Shift register 8 is similar to shiftregisters 2 and 5 so that parallel data of n bits are supplied to athird frame synchronizing signal detection circuit or detector 9 whereinthe frame synchronizing signal is detected when it is delayed by twoframe periods with respect to the reproduced digital data.

Frame synchronizing signal detection signals F₀, F₁, and F₂ generated,respectively, by frame synchronizing signal detectors 3, 6 and 9, aresupplied to a majority logic circuit 10. Majority logic circuit 10supplied an output signal F_(A) when two or more of the three framesynchronizing signal detection signals F₀, F₁, and F₂ coincide. When therotational speed of the disc is steady, frame synchronizing signaldetectors 3, 6, and 9 produce frame synchronizing signals F₀, F₁ and F₂at coincident frame cycles or periods. When the phases of framesynchronizing signal detection signals F₀, F₁, coincide, majority logiccircuit 10 produces output signal F_(A) for each frame period.

If two or more frame synchronizing signals successively drop out of thedigital signal, the phases of two or more of frame synchronizing signaldetection signals F₀, F₁, and F₂ do not coincide at the time when thedrop outs occur, so that majority logic circuit 10 does not produceoutput signal F_(A). The frame synchronizing signal is thus not properlydetected.

Clock generator 13 supplies clock pulses CP to a clock terminal of acounter 11. Counter 11 produces a carry pulse F_(C) in response to theclock pulses CP counted during one frame period. Accordingly, carrypulse F_(C) has a period corresponding to the frame period of thereproduced digital signal. Counter 11 produces a signal for each frameperiod even when majority logic circuit 10 does not generate outputsignal F_(A), the frame synchronizing signal detection signal with thecorrect period. If Majority logic circuit 10 produces a framesynchronizing signal detection signal with the correct period, counter11 is reset thereby so that the phase of carry pulse F_(C) coincideswith the detected frame synchronizing signal.

Carry pulse F_(C) is supplied to one input terminal of an OR gate 12.Output signal F_(A) is supplied to another input terminal of OR gate 12.OR gate 12 produces a frame synchronizing signal detection signal F_(G)if the frame synchronizing signal from majority circuit 10 is correct.Carry pulse F_(C) from counter 11 is supplied through OR gate 12 tooutput terminal 14 as signal F_(G) when the frame synchronizing signalis not generated by majority circuit 10 due, for example, to a drop out.

In FIG. 1, it is to be appreciated that the reproduced digital data isgenerated at output terminal 15.

A digitally recorded signal on a disc must be synchronized in a bit-wisefashion with a clock signal in the reproducing apparatus for thereproduction to be performed. When the clock signal and the reproducedsignal deviate in phase from each other, and the phase deviation isadded thereto, a cycle slip phenomenon can occur in which the framesynchronizing signal from one cycle period is dropped and/or changed inposition. In a bit synchronizing circuit, the frequency of a variablefrequency oscillator in a phase locked loop (PLL) circuit and the timeconstant of a low-pass filter are selected so that a time error causedby the cycle slip phenomenon is kept to about ±1 or 2 bits.

The operation of the circuit of FIG. 1 will now be described withreference to the timing charts of FIGS. 2A to 2F, 3A to 3F, and 4A to4F.

In FIG. 2A, the period between the third and fourth frame synchronizingsignals is shortened due to the cycle slip phenomenon, while the seventhand eighth frame synchronizing signals disappear due to drop outs. (Theperiods identified by the X marks in FIGS. 2A to 2F indicate periodshaving erroneous lengths.)

As illustrated in FIG. 2D, output signal F_(A) from majority logiccircuit 10 is generated at the timing of the fourth frame synchronizingsignal since frame synchronizing signal detection signal F₁ from framesynchronizing signal detector 6 has the same phase as framesynchronizing signal detection signal F₂ from frame synchronizing signaldetector 9. Output signal F_(A) from majority logic circuit 10 isgenerated at the timing of the fifth frame synchronizing signal sinceframe synchronizing signal detection signals F₀ and f₁ are in phase.

Counter 11 is reset by output signal F_(A) from majority logic circuit10 and produces carry pulse F_(C), as shown in FIG. 2E. Counter 11 doesnot generate signal F_(C) in the fifth frame period because the periodbetween the fourth and fifth signals is shorter than the normal frameperiod. Thus, counter 11 is reset by output signal F_(A) before itgenerates carry pulse F_(C).

Output signal F_(A) from majority logic circuit 10 and carry pulse F_(C)from counter 11 are supplied to OR gate 12 which supplies output signalF_(G) as the frame synchronizing signal detection signal, as shown inFIG. 2F. As is clear from the time charts, the frame synchronizingsignal for the drop out period is produced by carry pulse F_(C) with aframe period derived from counter 11.

FIGS. 3A to 3F illustrate a digital signal in which cycle slip occursbetween the third and fourth frame synchronizing signals and the lengthof the period accordingly becomes longer than one frame period, and inwhich drop outs occur in the seventh and eighth frame periods.

Since the length of the cycle slip is longer than one frame period,counter 11 is not reset before it generates carry pulse F_(C). Carrypulse F_(C) for the frame period is generated (as shown in FIG. 3E), butcounter 11 is reset by output signal F_(A) from majority logic circuit10 during the period between the generation of the first carry pulseF_(C) and the following carry pulse F_(C) so that the periodtherebetween corresponds to the length of the cycle slip, i.e. is lowerthan one frame period. FIG. 3F illustrates frame synchronizing signaldetection signal F_(G) supplied at output terminal 14.

FIGS. 4A to 4F illustrate a digital signal in which the noise therein ismixed with the frame synchronizing signal to form a doubtful framesynchronizing signal. FIGS. 4A to 4F also illustrate the digital signalfrom a reproducing apparatus operated in the search mode wherein theframe synchronizing signals are not detected by the frame synchronizingsignal detectors 3, 6, 9.

In FIGS. 4A to 4C, the doubtful frame synchronizing signal does notoverlap at the same position in frame synchronizing signal detectionsignals F₀, F₁ and F₂, so that majority logic circuit 10 produces outputsignal F_(A) (as shown in FIG. 4D) without the doubtful framesynchronizing pulse.

When the reproducing apparatus is operated in the search mode, and theframe synchronizing signal is not detected, counter 11 produces signalF_(C) for each frame period and which is supplied to output terminal 14as frame synchronizing signal detection signal F_(G). After the searchmode of operation has ended, majority logic circuit 10 generates outputsignal F_(A) at a position for the second frame synchronizing signal, ascounted from the end of the search mode, whereby counter 11 is resetbefore carry pulse F_(C) is generated again. As shown in FIG. 4E, thecorresponding frame period is longer than one frame period. A framesynchronizing signal detection signal F_(G) is generated at outputterminal 14, as shown in FIG. 4F. In other words, a signal indicatingthe correct frame period is generated immediately after the terminationof the search mode.

The circuit of FIG. 1, however, suffers from significant drawbacks.First, the circuit requires a memory unit which operates at high speed.Second, majority logic circuit 10 cannot remove a doubtful framesynchronizing pulse which repeatedly occurs at the same position in eachframe period.

Several points must be considered in a frame synchronizing signaldetecting and compensating circuit. First, a cycle slip which occurs inthe reproduced digital signal is normally about ±1 or 2 bits, and isquite small when compared with the length of the frame period. Second,since the pattern for the frame synchronizing signal is especiallyselected, a safe region must be provided before and after the framesynchronizing signal so that it can be accurately detected. Third, thepattern for the frame synchronizing signal is not a pattern whichordinarily occurs in the modulation system so that as long as a drop outand a doubtful frame synchronizing signal are not mixed, the probabilityof the same pattern randomly occurring in the digital signal isapproximately zero.

There are at least two known methods by which an audio pulse codedmodulation (PMC) signal can be recorded on a disc. According to onemethod, the PCM signal is recorded with a constant angular velocity. Inan alternate method, the PCM signal is recorded with a constant linearvelocity. Recordings made with a constant linear velocity are preferableto recordings made with a constant angular velocity because therecording density for such recordings can be increased. In such aninstance, the disc on which the recording is made must be reproduced ata constant linear velocity.

One known method for controlling disc rotation at a constant linearvelocity detects the position of a pick-up device by a potentiometer.Since the disc must rotate faster as the pick-up device moves away fromthe center of the disc, the output signal from the potentiometer is fedto a divided circuit to generate speed control information from theposition of the pick-up device. However, a potentiometer and a dividercircuit for generating the speed control signals are both expensive andcomplicated.

According to another method, the disc is rotated at a constant linearvelocity by detecting a reproduced signal from the disc. The length oftime for a transition interval is measured and compared with a standardreference value. The speed of the disc is then changed according to thecomparison.

When a disc is reproduced at a constant linear velocity, a minimumtransition interval T_(min) and a maximum transition interval T_(max) inthe reproduced signal assume predetermined reference values. Therefore,if the maximum transition interval T_(max) or the minimum transitioninterval T_(min) in the reproduced signal deviates from the referencevalue, the rotational speed can be controlled to reduce or eliminate thedeviation, so that the disc rotates at a constant linear velocity.

Since the frame synchronizing signal is reproduced at each frame period,a velocity control circuit can be operated so that successive maximumtransition intervals T_(max), which are the frame synchronizing signals,assume a predetermined value.

In FIG. 5, a PCM audio disc reproducing apparatus includes a velocitycontrol system 100, a phase control system 200, and a framesynchronizing signal detecting and compensating circuit 300 in accordwith the present invention. Frame synchronizing signal detecting andcompensating circuit 300 generates a detection signal in response to aframe synchronizing signal and compensates for drop outs, cycle slips,or the like. Compensating circuit 300 also generates a signal whichdetermines whether the operation of phase control system 200 is added tovelocity control system 100.

In velocity control system 100, an optional pick-up device 101 generatesa signal which is supplied to a wave shaping circuit 102. The outputsignal from optical pick-up device 101 can be blunted or rounded. Forexample, a sinusoidal wave may be generated in response to data bits of"1" and "0". Wave shaping circuit 102 reshapes the signal from opticalpick-up device 101 and delivers a substantially square wave in responseto the blunted input wave.

A counter 103 detects the maximum transition interval T_(max). A clockpulse CP having a frequency of, for example, about 34.6 MHz andgenerated by an oscillator 104 is supplied to a clock terminal CK ofcounter 103. An output signal SP from wave shaping circuit 102 issupplied to a clear terminal CL of counter 103 through a NAND gate 105and an AND gate 107 whereby counter 103 is cleared at the falling ortrailing edge of output signal SP. Output signal SP is supplied to aninverter 108 which supplies an output signal SP to a clear terminal CLof counter 103 by way of a NAND gate 106 and AND gate 107 wherebycounter 103 is also cleared at the rising or leading edge of outputsignal SP. Counter 103 thus counts the number of clock pulses CP duringthe respective position and negative polarity transition intervals ofoutput signal SP.

When output signal SP has a transition interval in which the number ofclock pulses CP counted therein exceeds a predetermined number N (whereN is a value counted during maximum transition interval T_(max)),counter 103 generates output signals of "1" at its Q output terminals.The output signals from the Q terminals of counter 103 are supplied to aNAND gate 109 which then generates an output signal N₀ having a value of"0" when the output signals from counter 103 are "1". Output signal N₀is supplied to an enable terminal EN of counter 103, so that counter 103stops the counting operation. Since output signal N₀ is also supplied toNAND gates 105 and 106, NAND gates 105 and 106 are turned off. Counter103 cannot e cleared by a reproduced digital signal thereafter.

Output signal N₀ from NAND gate 108 is latched to a D-type flip-flopcircuit 110 in response to the rising edge of a signal SFX. A quartzoscillator 111 supplied an output clock pulse to frequency divided 112which divides the output clock pulses to generate signal SFX. In theillustrative embodiment, signal SFX has a frame period of 1/7.35 kHz.

After output signal N₀ from NAND gate 109 is latched to D-type flip-flopcircuit 110 as described above, signal SFX is supplied to a clearterminal CL of counter 103 through a delay circuit 113 and AND gate 107whereby counter 103 is cleared. Output signal N₀ from NAND gate 109becomes "1" to place counter 103 in a count enable state and NAND gates105 and 106 in an open state. Thus, the number of clock pulses CPcounted during the transition intervals of the output signal SP arecounted again.

Accordingly, counter 103 detects whether the maximum transition intervalT_(max) in the output signal SP is longer or shorter than a referencevalue for each frame period. The output signal from counter 103 islatched to D-type flip-flop circuit 110 after being supplied to NANDgate 109. If counter 103 detects that any one of the transitionintervals of output signal SP is longer than the reference value for oneframe period, output signal N₀ from NAND gate 109 becomes "0". When therespective transition intervals of output signal SP are shorter than thereference value, output signal N₀ from NAND gate 109 becomes "1". Theoutput signal before the detection of the maximum transition intervalT_(max) is stored in D-type flip-flop circuit 110 during the succeedingframe period.

A charge and discharge circuit 120 includes a capacitor 121 for chargeand discharge, a positive current source 122 and a negative currentsource 123. When an output signal VS from the Q terminal of D-typeflip-flop circuit 110 is "0", and an output signal VS from Q outputterminal of D-type flip-flop circuit 110 is "1", a switching circuit 124is switched on so that a charging current i_(v+) is supplied tocapacitor 121 from positive current source 122. When output signal VSfrom the Q terminal of D-type flip-flop circuit 110 is "1", and outputsignal VS at Q output terminals of D-type flip-flop circuit 110 is "0",a switching circuit 125 is switched on so that capacitor 121 permits adischarging current i_(v-) to flow through negative current source 123.

Accordingly, capacitor 121 is charged and discharged in response to theoutput signals from D-type flip-flop circuit 110. The voltage developedacross capacitor 121 is supplied to an inverting input terminal of anoperational amplifier 130 which operates as a comparator. A positive DCvoltages ES is supplied to a non-inverting input terminal of operationalamplifier 130. A difference output signal from operational amplifier 13is supplied to a motor driving circuit (not shown) for rotating thedisc.

When the rotational speed of the disc is slower than a predeterminedlinear velocity, the maximum transition interval T_(max) in outputsignal SP is longer than the reference value. Output signal N₀ from NANDgate 109 becomes "0", switching circuit 124 is switched on whileswitching circuit 125 is switched off so that charging current i_(v+)flows to capacitor 121. Since the voltage across capacitor 121increases, the output voltage from operational amplifier 130 decreases,so that the rotational speed of the motor increases.

When the rotational speed of the disc is higher than a predeterminedlinear velocity, the maximum transition interval T_(max) in thereproduced signal SP is shorter than the reference value, so that theoutput signal N₀ from NAND gate 109 becomes "1" during each frameperiod. Switching circuit 125 is switched on to permit dischargingcurrent i_(v-) to flow from capacitor 121. The voltage across capacitor121 is accordingly lowered, the output voltage from operationalamplifier 130 increases, and the rotational speed of the motordecreases.

When the disc rotates at a constant linear velocity, the voltage acrosscapacitor 121 is reduced substantially to zero.

A diode 126 (with a cathode connected to ground) is connected inparallel to capacitor 121 to prevent the motor from rotating in areverse direction. When a potential at a point P in FIG. 5 is a positivevoltage and exceeds reference voltage ES, the output signal fromoperational amplifier 130 approaches a negative voltage so that themotor would begin to rotate in a reverse direction. However, since diode126 is connected between point P and ground, it is switched on. Hence,the potential at point P does not become positive, and the motor doesnot rotate in a reverse direction.

With reference to phase control system 200, signal SFX has a referenceframe period which is produced by dividing the frequency of the outputsignals from quartz oscillator 111 in frequency divider 112. Signal SFXcan form a constant phase relationship with a signal SFG which issyrnchronized with the frame synchronizing signal SF detected in thereproduced signal by frame synchronizing signal detecting andcompensating circuit 300. The lock frequency for phase control system200 is a function of the oscillation frequency generated by quartzoscillator 111. In the illustrative embodiment, the oscillationfrequency of quartz oscillator 111 is selected so that when the maximumtransition interval T_(max) is the reference value and the velocitycontrol is stable, phase control system 200 is locked.

Signal SFX is supplied to a flip-flop circuit 210 which generates asignal F₁ which is inverted at the leading edge of signal SFX. A signalSFG, having a frame period derived from frame synchronizing signaldetecting and compensating circuit 300, is supplied to a flip-flopcircuit 202 which generates a signal F₂ which is inverted at the leadingedge of signal SFG. Signals F₁ and F₂ are supplied to input terminals ofan AND gate 203 which generates an output signal A₁ indicative of thedifference in phase between output signals F₁ and F₂. Output signal A₁is supplied to the input terminals of AND gates 205 and 206.

Signal F₂ from the Q output terminal of flip-flop 202 is supplied to a Dterminal of a D-type flip-flop circuit 204. Signal F₁ from the Qterminal of a D-type flip-flop 210 is supplied to clock terminal CK offlip-flop circuit 204. An output signal UD from the Q output terminal offlip-flop 204 is supplied to one input terminal of an AND gate 205.Output signal UD is also supplied to an inverter 207 which supplies itsoutput to an AND gate 206.

AND gate 205 supplies an output signal A₂ to a charge and dischargecircuit 210. AND gate 206 supplies an output signal A₃ to charge anddischarge circuit 210.

Charge and discharge circuit 210 generates a phase control voltage inresponse to output signals A₂ and A₃ and includes a capacitor 211 forcharge and discharge, a positive current source 212, and a negativecurrent source 213. When output signal A₂ from AND gate 205 is "1", aswitching circuit 214 is switched on so that positive current source 212permits a charging current i_(p+) to flow to capacitor 211. When outputsignal A₃ from AND gate 206 is "1", a switching circuit 215 is switchedon so that capacitor 211 permits a discharging circuit i_(p-) to flowthrough negative current source 213.

As illustrated in FIGS. 6L and 6M, when signals F₁ and F₂ have a phasedifference of 180°, signals SFX and SFG have no phase differencetherebetween. Output signal A₂ from AND gate 205 becomes "0" at alltimes. Phase control system 200 operates so that signals SFX and SFGmaintain a predetermined phase relation therebetween.

When signals SFX and SFG have the phase relationship depicted in FIGS.6A and 6C, and output signals F₁ and F₂ from flip-flop circuits 201 and202 have a 180° phase difference as illustrated in FIGS. 6B and 6D,output signal UD from flip-flop circuit 204 becomes "0", as shown inFIG. 6F. Output signal A₁ from AND gate 203 has the displacement shownin FIG. 6E.

Although output signal A₂ from AND gate 205 becomes "0", as shown inFIG. 6G, AND gate 206 produces a signal having a width dependent on thephase deviation which is shown in FIG. 6H and identified as outputsignal A₃. Switching circuit 215 is switched on to allow a dischargingcurrent i_(p-) to flow from capacitor 211 whereby the voltagethereacross decreases.

When signals SFX and SFG deviate in phase with respect to each other, asindicated in FIGS. 6A and 6C, the width of output signal A₁ from ANDgate 203 does not change, but output signal UD from D-type flip-flop 204becomes "1", as illustrated in FIG. 6I. Output signal A₂ of AND gate 205has a width representative of the phase deviation as shown in FIG. 6G sothat switching circuit 214 is switched on and switching circuit 215 isswitched off thereby permitting a charging current i_(p+) to flow tocapacitor 211 whereby the voltage thereacross increases.

The voltage across capacitor 211 is added to the output voltage fromcharge and discharge circuit 120 in velocity control system 100 and thensupplied to the inverting input terminal of operational amplifier 130where it controls the speed of the motor.

In the illustrated embodiment, charge and discharge circuit 120 has atime constant T_(V) and charge and discharge circuit 210 has a timeconstant T_(P). Time constants T_(V) and T_(P) are selected whereby:

    T.sub.V >T.sub.p

so that in a stationary state, velocity control circuit 100 controlslarge changes in the rotational speed of the disc, while phase controlcircuit 200 controls small changes in the rotational speed of the disc.It is to be appreciated that the disc rotates with nominal wow andflutter because of the circuit arrangement of the present invention.

Signal SFG generates a phase control signal and is derived from framesynchronizing signal detecting and compensating circuit 300 by frequencydividing an output signal of a PLL circuit which is synchronized withthe clock component in the reproduced digital signal. The PLL circuit offrame synchronizing signal detecting and compensating circuit 300 has alimited lock range so that until the rotational speed of the disc isapproximately equal to a predetermined linear velocity, the phasecontrol system 200 cannot be brought into operation. It is to beappreciated that the rotational speed of the disc cannot be locked inphase with the output signal from quartz oscillator 111 following alarge fluctuation in the linear velocity of the disc which can occurwhen the pick-up device scans the disc. Accordingly, phase controlsystem 200 is disabled until the linear velocity of the disc becomessubstantially constant.

In order to detect the frame synchronizing signal, a clock pulse issynchronized with the clock component in the reproduced digital signaland the bit pattern resulting therefrom is compared with the bit patternfrom the frame synchronizing signal in the reproduced digital signal. Inthe illustrative embodiment, the output signal from the PLL circuit asdescribed above is used for the clock pulse. Accordingly, when thelinear velocity has not reached the predetermined speed, the PLL circuitis not locked in phase with the reproduced clock signal and the framesynchronizing signal cannot be reliably detected.

Frame synchronizing signal detecting and compensating circuit 300 thusincludes a supervisory circuit which keeps a close watch on whether theframe synchronizing signal is reliably detected. Output signal SL(derived from frame synchronizing signal detecting and compensatingcircuit 300) is at a high level when the frame synchronizing signal isnot reliably detected, as described hereinbelow. Output signal SL issupplied to AND gates 205, 206 through an inverter 208 so that until thelinear velocity of the disc reaches a predetermined value, AND gates 205and 206 are turned off by output signal SL, thereby inhibiting theoperation of phase control system 200.

FIG. 7 illustrates one embodiment of a frame synchronizing signaldetecting and compensating circuit 300 in accord with the presentinvention. Signal SP, such as digital data or the like, from waveshaping circuit 102 (see FIG. 5) is supplied to an input terminal 301and thence, to a frame synchronizing signal detection circuit ordetector 302. A clock pulse CP is synchronized with the reproducedsignal derived from a clock generator 308 which includes a PLL circuitand is supplied to detector 302. Detector 302 generates a framesynchronizing signal detection signal SFO by detecting a signal having abit pattern which is the same as the frame synchronizing signal in thereproduced signal as described hereinbefore. Frame synchronizing signaldetection signal SFO is supplied to a protecting circuit 303 which mutesframe synchronizing detection signal SFO to prevent noise from beingerroneously detected as a frame synchronizing signal. Protecting circuit303 is most commonly utilized in the period during playback when theposition of the pick-up device jumps and there is no reproduced signal.Protecting circuit 303 may be eliminated from the circuit of FIG. 7 andthe circuit will operate as herein described.

Frame synchronizing signal detection signal SFO is supplied throughprotecting circuit 303 to a gate circuit 304. A window pulse PW suppliedfrom an OR gate 305 functions as a gate signal for gate circuit 304. Inone embodiment, window pulse P has a pulse width of 2 m bits (m bits±the position at which a normal frame synchronizing signal occurs). Inone example, m can be equal to three. When a frame synchronizing signaloccurs at the correct position and the phase of window pulse PWsubstantially coincides therewith, gate circuit 304 supplies a detectionsignal SFW to an OR gate 306. Detection signal SFW is also supplied to aclear terminal CL of a counter 307. A clock pulse CP is supplied to aclock terminal of counter 307. Clock pulse CP is synchronized with theclock component of the reproduced signal and is derived from a clockgenerator 308 equipped with a PLL circuit so that counter 307 generatesa carry pulse SFC for each frame period. Carry pulse SFC is synchronizedwith the reproduced signal which results from dividing the frequency oflock pulse CP and is supplied to one input terminal of OR gate 306. ORgate 306 supplied a frame synchronizing signal detection signal SFG, asdescribed more fully hereinbelow, to an output terminal 317.

Window pulse PW is generated in response to the count value from counter307. When the count value "n" in counter 307, which corresponds to theframe period, is reduced by a number corresponding to m bits of themaximum value of a cycle slip (for example 3 bits), the reduced countnumber n-m is detected by an "n-m" detector 309 and a flip-flop circuit310 is accordingly set. When the count value of counter 307 correspondsto m bits, such count number is detected in an "m" detector 311 so thatflip-lop circuit 310 is set. Since counter 307 is cleared by detectionsignal SFW, flip-flop circuit 310 generates a window signal which risesat a position m bits before the frame synchronizing signal occurs andwhich falls m bits after the trailing edge of the frame synchronizingsignal. The window signal is supplied to one input terminal of OR gate305 and comprises window pulse PW for gate circuit 304.

Gate circuit 304 does not generate detection signal SFW when the phaseof the frame synchronizing signal significantly deviates from carrypulse SFC. A supervisory circuit (explained more fully hereinbelow)detects the phase displacement between the frame synchronizing signaland carry pulse SFC and forces counter 307 to make the framesynchronizing signal coincide in phase with carry pulse SFC.

Supervisory counter 312 comprises in part the abovedescribed supervisorycircuit. Detection signal SFW is supplied to a load terminal LD ofsupervisory counter 312 to preset the counter value therein. An outputsignal from "m" detector 311 is supplied to a clock terminal ofsupervisory counter 312 when the count value from counter 307corresponds to m bits.

Since counter 307 counts the number of clock pulses CP at all times, "m"detector 311 generates a signal at each frame period which is suppliedto and counted by supervisory counter 312. Gate circuit 304 generatesdetection signal SFW which is supplied to load terminal LD ofsupervisory counter 312 so that supervisory counter 312 is preset. It isto be appreciated that the count value in supervisory counter 312 doesnot increment more than the preset value plus one. When gate circuit 304does to generate detection signal SFW, supervisory counter 312 countsthe output signal from "m" detector 311 so that the count value thereinincrements. When the count value of supervisory counter 312 reaches apredetermined value (for example, eight), supervisory counter 312generates an output signal SL which rises to a high level. Since outputsignal SL is supplied to an enable terminal EN of supervisory counter312, the counting operation of supervisory counter 312 stops. Outputsignal S1 from supervisory counter 312 is also supplied to gate circuit304 as window pulse PW via OR gate 305. In other words, the gate signalremains at a high level to keep gate circuit 304 in an open state.

When gate circuit 304 generates detection signal SFW, supervisorycounter 312 is placed into a load state again whereby output signal SLdrops to a low level and supervisory counter 312 returns to a countenable state.

Functionally, when the phase of carry pulse SFC deviates considerablyfrom the phase of the frame synchronizing signal in the reproducedsignal so that frame synchronizing signal detection signal SFO does notfall within the width of winding pulse PW, supervisory counter 312detects such deviation and permits counter 307 to be cleared whereby thephase of carry pulse SFC is made to coincide with the framesynchronizing signal in the reproduced signal. (In the illustrativeembodiment, supervisory counter 312 can be a preset type or an ordinaryclear-type counter.)

In accord with the present invention, the width of window pulse PW andthe preset value for supervisory counter 312 are controlled in accordwith the operating mode of the reproducing apparatus and state of thereproduced signal so that the compensating circuit will operate mostefficiently.

In a normal playback mode, the width of window pulse PW is such that itwill gate the frame synchronizing signal detection signal even when acycle slip occurs. For example, the frame synchronizing signal can bewithin ÷3 bits of the position where it is expected to be detected. Thewidth of ±3 bits is generally acceptable in a normal playback mode whenthe data error in the reproduced signal is random. However, when thereare a large number of burst errors in the reproduced signal, the amountof cycle slip increases since the amount of the phase deviation betweenthe reproduced signal and the clock signal accumulates. The width ofwindow pulse PW must be correctly widened.

Supervisory counter 312 corrects phase deviations between window pulsePW and frame synchronizing signal detection signal SFO. When the framesynchronizing signal is reliably detected, as in a normal playback mode,the phase of window pulse PW is correct even if detection signal SFWdisappears as a result of a drop out or the like. If the supervisorycircuit operates under such conditions, the width of window pulse PW issubstantially increased. Noise, such as a doubtful frame synchronizingsignal and the like, cannot be eliminated, however. Accordingly, thenumber of frames required to be detected before output signal SL risesto the high level is relatively large, for example, sixteen. It is to beappreciated that the number of frames required to raise output signal SLto the high level is the same as the number of output signals generatedby "m" detector 311.

When the reproducing apparatus is operated in a search mode to accessthe beginning of a recording, output signal SL rises to a high levelshortly after the frame synchronizing signal is no longer detected. Inthe illustrative embodiment, output signal SL rises to a high levelafter three frame periods.

When the reproduced signal disappears during playback, supervisorycounter 312 raises output signal SL to a high level immediately afterthe frame synchronizing signal disappears. In addition, the rotationalspeed of the disc is controlled when the reproduced signal disappears sothat the width of window pulse PW is increased to its maximum.

The supervisory circuit in accord with the present invention includes anRF detector 313 which detects the presence of a reproduced signal andsupplies a detected output signal to a controller 316. A systemcontroller 314 supplies a signal to controller 316 which indicates theoperating mode of the reproducing apparatus. An error correction circuit315 detects errors in the reproduced signal and supplies a signalindicative of the errors to controller 316.

Controller 316 supplies control signal to "n-m" detector 309 and "m"detector 311 to vary the count value corresponding to the "m" bits. Thevalue of m and the corresponding width of window pulse PW vary in accordwith the errors detected in the digital signal by error correctioncircuit 315.

Controller 316 supplies an output signal to vary the preset value ofsupervisory counter 312 in accord with the operating mode of thereproducing apparatus and the presence of a reproduced signal detectedby RF detector 313.

The operation of the frame synchronizing signal detecting andcompensating circuit of FIG. 7 will now be described with reference tothe timing charts of FIGS. 8, 9 and 10. In FIGS. 8A to 8E, the digitalsignal supplied to the circuit of FIG. 7 has a frame period which isshorter than a normal frame period because of a cycle slip, and also hasdrop outs in the seventh and eighth frames. FIG. 8A illustrates framesynchronizing signal detection signal SFO from frame synchronizingsignal detector 302. FIG. 8B illustrates window pulse PW generated byflip-flop circuit 310. FIG. 8C illustrates detection signal SFWgenerated by gate circuit 304. FIG. 8D illustrates carry pulse SFCgenerated by counter 307. FIG. 8E illustrates frame synchronizing signaldetection signal SFG generated by OR gate 306.

In FIG. 8, the amount of cycle slip is small when there are a largenumber of random errors in the reproduced signal and a relatively smallnumber of burst errors. The amount of cycle slip is much greater whenthere are many burst errors. The width of window pulse PW variesaccording to the number of errors in the signal so that the detectionsignal for the frame synchronizing signal is substantially certainlycontained within the width of window pulse PW even considering the cycleslip. Gate circuit 304 generates detection signal SFW to clear counter307 before carry pulse SFC is generated so that the width of windowpulse PW is narrowed. Accordingly, carry pulse SFC is dropped during theperiod where the cycle slip occurs, as shown in FIG. 8D. During theperiod where the drop outs occur, a frame synchronizing signal is notdetected within the width of window pulse PW, so that gate circuit 304does not generate detection signal SFW. However, if counter 307 iscorrectly cleared by one detection signal SFW before the drop outsoccur, counter 307 generates carry pulse SFC having the correct frameperiod. Carry pulse SFC is then supplied through OR gate 306 to outputterminal 317 as frame synchronizing signal detection signal SFG.

In FIGS. 9A to 9E, the digital signal supplied to the circuit of FIG. 7contains a cycle slip and drop outs in the seventh and eighth periods.The period length exceeds the normal frame period because of the cycleslip. Detection signal SFW from gate circuit 304 clears counter 307after counter 307 has generated carry pulse SFC so that the timing ofcarry pulse SFC differs from the normal timing. As illustrated in FIG.9E, frame synchronizing signal detection signal SFG supplied at inputterminal 317 has double frame synchronization signals as a result of thecycle slip.

In FIG. 10A, the digital signal supplied to the circuit of FIG. 7includes a doubtful frame synchronizing signal mixed with the framesynchronizing signal, and a drop out in the fourth period. In addition,the reproducing apparatus is operated in a search mode to access thebeginning of an audio signal, during which time frame synchronizingsignal detection signal SFO drops out. The doubtful frame synchronizingsignal does not fall within the width of window pulse PW so that thedoubtful frame synchronizing signal is eliminated, and gate circuit 304delivers a correctly timed detection signal SFW. During the search modeof operation of the reproducing apparatus, gate circuit 304 does notgenerate a detection signal SFW in response to output signal SL fromsupervisory counter 312. As noted before, supervisory counter 312generates output signal SL when three frame synchronizing signals havebeen omitted. Gate circuit 304 is thus opened by output signal SL, asindicated in FIG. 10F. When the reproducing apparatus is operated in thenormal playback mode, after operation in the search mode, gate circuit304 generates detection signal SFW which places supervisory counter 312into the load mode and clears counter 307. Carry pulse SFC becomesdiscontinuous just after the search mode is terminated, as illustratedin FIG. 10D, but is correctly synchronized shortly thereafter.

As hereinbefore described, frame synchronizing signal detecting andcompensating circuit 300 produces frame synchronizing signal detectionsignal SFG even when a drop out in the digital signal occurs. Framesynchronizing signal detecting and compensating circuit 300 alsoproduces output signal SL to indicate whether the frame synchronizingsignal has been reliably detected. As explained above, output signal SLdetermines whether phase control system 200 is added to velocity controlsystem 100.

It is to be appreciated that a frame synchronizing signal detecting andcompensating circuit in accord with the present invention does notrequire a memory with a large capacity or the like.

As will be evident from the discussion hereinbefore, when an erroneousframe synchronizing signal occurs at the same position duringconsecutive frame periods, such erroneous signal can be removed sincethe frame synchronizing signal detection signal is gated by a gate pulsewhich is wide enough to accommodate the correct frame synchronizingsignal but narrow enough to eliminate the erroneous signal.

The compensating circuit in accord with the present invention alsocompensates for a dropped frame synchronizing signal when thereproducing apparatus is operated in the playback mode.

The compensating circuit in accord with the present invention furtherprevents an incorrect or arbitrary addition of the phase control systemto the velocity control system used in determining the rotational speedof the disc since the phase control system is added to the velocitycontrol system in response to a signal from a supervisory circuit whichkeeps watch on whether the frame synchronizing signal is reliablydetected.

It is to be further appreciated that the supervisory circuit operatesimmediately when the reproducing apparatus is operated in the playbackmode and also in response to the state of the reproduced signal.Accordingly, the speed control system for the reproducing apparatus canbe correctly operated since the output signal from the supervisorycircuit is used to control the addition of the phase control system tothe velocity control system.

The present invention is not limited to a reproducing apparatus for apulse coded modulation audio disc, but can be applied to any apparatuswhich reproduces a digital signal recorded in the base band and which,upon reproduction, has a frame or block synchronizing signal.

Although a specific embodiment of the present invention has beendescribed in detail herein with reference to the accompanying drawings,it is to be understood that the invention is not limited to that preciseembodiment, and that various changes and modifications may be effectedtherein by one skilled in the art without departing from the spirit andscope of the invention as defined in the appended claims.

What is claimed is:
 1. In a detecting and compensating circuit of anapparatus for reproducing a digital signal separated by framesynchronizing signals, each having a predetermined frame period, thecombination comprising:detecting means for detecting said framesynchronizing signals and generating respective detection signals inresponse thereto; gating means receiving said detection signals forgating the latter in response to gating signals; and windowing meansincluding first means for supplying first window signals of a firstpredetermined length synchronized with said detection signals as saidgating signals to said gating means, and second means for supplyingsecond window signals of a second predetermined length as said gatingsignals to said gating means when a plurality of .[.said.]. .Iadd.gated.Iaddend.detection signals are not .[.generated.]. .Iadd.output by saidgating means, .Iaddend.said second predetermined length being greaterthan said first predetermined length.
 2. The circuit of claim 1; whereinsaid second means includes supervisory means for detecting deviations inphase between said first window signals and said detection signals .[.asgated by said gating means.]. and for supplying said second windowsignals to said first means to vary the timing of said first windowsignals in the sense to correct said deviations therebetween.
 3. Thecircuit of claim 2; and wherein said apparatus for reproducing has aservo circuit responsive to said second window signals supplied by saidsupervisory means for operating said apparatus for reproducing at apredetermined speed suitable for said reproducing of said digitalsignal.
 4. The circuit of claim 3, wherein said servo circuit includesspeed control means for effecting small changes in said operating speedof said apparatus, and wherein said second window signals from saidsupervisory means selectively actuate said speed control means.
 5. Thecircuit of claim 1; wherein said first means includes:clock means forgenerating clock signals corresponding to said frame periods of saiddigital .[.signals.]. .Iadd.signal .Iaddend.and counter means forcounting said clock signals and for generating said first window signalswhen a count derived therefrom .[.exceeds a.]. .Iadd.corresponds to.Iaddend.predetermined .[.value.]. .Iadd.values. .Iaddend.
 6. Thecircuit of claim 5; wherein said detection signals gated by said gatingmeans reset said counter means to a predetermined value.
 7. The circuitof claim 5; wherein said windowing means includes means for determiningsaid predetermined length of said first window signals.
 8. The circuitof claim 7; wherein said means for determining includes:means fordetermining a beginning time of each of said first window signals andfor generating a beginning signal in response thereto; and means fordetermining an end time of each of said first window signals and forgenerating an end signal in response thereto.
 9. The circuit of claim 8,wherein said means for determining a beginning time is connected to saidclock means and generates a count corresponding to said predeterminedframe period less one-half of said predetermined length of said firstwindow signals to determine said beginning signal, and wherein saidmeans for determining an end time is connected to said clock means andgenerates a count corresponding to one-half of said predetermined lengthof said first window signals to determine said end signal.
 10. Thecircuit of claim 8, .Iadd.wherein said second means includes supervisorymeans for detecting deviations in phase between said first windowsignals and said detection signals and .Iaddend.in which said.Iadd.supervisory means includes .Iaddend.counter means .Iadd.that.Iaddend.receives clock signals for operation therewith; and whereinsaid end signals are supplied to said counter means as said clocksignals.
 11. The circuit of claim 7; wherein said first means includesgenerating means connected to said means for determining for generatingsaid first window signals with said first predetermined length;.Iadd.said second means includes supervisory means for detectingdeviations in phase between said first window signals and said detectionsignals for supplying said second window signals; .Iaddend.and saidwindowing means includes OR gate means for receiving said .Iadd.firstand second .Iaddend.window signals from .[.both.]. said generating meansand said supervisory means.Iadd., respectively, .Iaddend.and forsupplying said window signals to said gating means.
 12. The circuit ofclaim 11; wherein said generating means is a flip-flop circuit.
 13. Thecircuit of claim 7; wherein said supervisory means includes controllermeans for supplying control signals to said means for determining tovary said first predetermined length of said first window signals. 14.The circuit of claim 13, in which said apparatus for reproducing isoperable in a plurality of modes; and further comprising systemcontroller means for supplying signals to said controller means to varysaid first predetermined length of said first window signals inaccordance with said modes of said apparatus for reproducing.
 15. Thecircuit of claim 13, in which said digital signal has a plurality ofstates; and further comprising RF detector means for detecting saidstates of said digital signal and supplying signals to said controllermeans to vary said predetermined length of said first window signals inresponse thereto.
 16. The circuit of claim 13; and further comprisingerror correction means for supplying signals to said controller means tovary said first predetermined length of said first window signals inresponse to errors in said digital signal. .[.
 17. The circuit of claim5; wherein said clock means includes:a clock generator for generatingclock pulses synchronized with said frame period; and counter means forcounting said clock pulses from said clock generator..]. .Iadd.
 18. In adetecting and compensating circuit of an apparatus for reproducing adigital signal separated into predetermined frame periods by framesynchronizing signals, the combination comprising:means for receiving areproduced digital signal; synch detector means for detecting the framesynchronizing signals from the reproduced digital signal and generatingdetection signals in response thereto; gating means receiving thedetection signals for gating the latter in response to window pulses fedthereto as a gating signal; clock means for generating clock signals;counter means for counting said clock signals up to a firstpredetermined number (n) corresponding to the predetermined frameperiod; window signal generating means including first detecting meansconnected to said counter means for detecting the count of said countermeans and generating gate-open signals when the count of said countermeans is equal to a second predetermined number that is less than thefirst predetermined number (n) at a first predetermined time followingoccurrence of the detection signals to determine a beginning time ofeach window pulse of the gating signal fed to said gating means; andsaid window signal generating means further including second detectingmeans connected to said counter means for detecting the count of saidcounter means and generating gate-close signals when the count of saidcounter means is equal to a third predetermined number less than thesecond predetermined number at a second predetermined time followingoccurrence of the detection signals to determine an end time of eachwindow pulse of the gating signal. .Iaddend. .Iadd.19. The circuit ofclaim 18; wherein each window pulse of the gating signal issubstantially centered relative to each of said detection signals fromsaid signal detector means. .Iaddend. .Iadd.20. The circuit of claim 18;wherein said window signal generating means includes a flip-flop circuitconnected to said first detecting means and said second detecting meansfor generating said window pulse. .Iaddend. .Iadd.21. The circuit ofclaim 18; wherein said window pulse has a predetermined initial lengthand said first detecting means generates said gate-open signals when thecount of said counter means corresponds to said predetermined frameperiod of less one-half of the predetermined initial length of saidwindow pulse and said second detecting means supplies the gate-closesignals when the count of said counter means corresponds to one-half ofthe predetermined initial length of said window pulse. .Iaddend..Iadd.22. The circuit of claim 21; further comprising controller meansfor supplying control signals to said window signal generating means fordetermining said first predetermined time. .Iaddend. .Iadd.23. Thecircuit of claim 22; wherein said apparatus reproduces said digitalsignal in different modes and said controller means determines saidfirst predetermined time in accordance with said different reproducingmodes of the reproduced signal. .Iaddend. .Iadd.24. The circuit of claim23; wherein said digital signal has a plurality of states, and furthercomprising third detecting means for detecting the state in which saiddigital signal is reproduced and supplying an output signal to saidcontroller means to determine the first predetermined time in responsethereto. .Iaddend. .Iadd.25. The circuit of claim 23; further comprisingerror correction means for detecting errors in the reproduced digitalsignal and supplying signals to said controller means to determine saidfirst predetermined time in response to detected errors in said digitalsignal. .Iaddend. .Iadd.26. In a detecting and compensating circuit ofan apparatus for reproducing a digital signal separated intopredetermined frame periods by frame synchronizing signals, thecombination comprising:detecting means receiving the reproduced digitalsignal for detecting said frame synchronizing signals and generatingdetection signals in response thereto; gating means receiving saiddetection signals for gating the latter in response to gating signals;windowing means including first means for supplying first window signalssynchronized with said detection signals from said detecting means assaid gating signals to said gating means and second means for supplyingsecond window signals of length longer than said first window signals assaid gating signals to said gating means in the absence of a pluralityof gated detection signals from said gating means; said second meansincluding means for detecting deviations in phase between said firstwindow signals and said detection signals gated by said gating means andproducing a corresponding output, and counter means receiving saidoutput from said means for detecting deviations for supplying saidsecond window signals to said gating means when a count in said countermeans exceeds a predetermined value. .Iaddend. .Iadd.27. The circuit ofclaim 26; in which said apparatus includes a plurality of operatingmodes and further comprising controller means for determining saidpredetermined value in said counter means in accordance with saidplurality of reproducing modes. .Iaddend. .Iadd.28. The circuit of claim26; wherein said apparatus includes a plurality of operating modes andsaid digital signal has a respective plurality of states, and furthercomprising RF detector means for detecting said states of said digitalsignal and controller means for determining said predetermined value insaid counter means in response to said detected states of said digitalsignal. .Iaddend. .Iadd.29. The circuit of claim 26; further comprisingcontroller means for determining said predetermined value in saidcounter means and error correction means for detecting errors in thereproduced digital signal and supplying signals to said controller meansto vary said predetermined value in response to errors in said digitalsignal. .Iaddend. .Iadd.30. The circuit of claim 26; wherein saidapparatus for reproducing includes a rotational speed control circuitresponsive to said second window signals supplied by said counter meansfor operating said apparatus at a predetermined speed for reproducingsaid digital signal. .Iaddend. .Iadd.31. The circuit of claim 30;wherein said rotational speed control circuit includes operating speedcontrol means for effecting changes in said predetermined speed of saidapparatus, and said second window signals from said counter meansselectively actuate said speed control means. .Iaddend.